Author

A. Zambanini

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Open access Sep 2026

Hardware-efficient neural networks for FPGA-based radio triggering of extensive air showers

We present a hardware-efficient hybrid trigger for FPGA-based radio detection of extensive air showers. The hybrid design consists of a lightweight denoiser that cleans raw ADC traces and a compact classifier that operates on the denoised output, enabling robust near-threshold pulse detection in high-interference envir...

Vesselin Dimitrov, Alperen Aksoy, Ilja Bekman et al. · Arena · 0 citations

Preprint Sep 2026

OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology

This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transisto...

Yang Chen, Daniele Storelli, Xin-Yi Zhao et al. · 0 citations