Author

Aditya Akella

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Book Open access Sep 2026

TierSizer: Counterfactual Reasoning for DRAM Sizing in Tiered Memory Systems

Compute Express Link (CXL) enables cost-effective memory capacity expansion by placing additional tiers behind a coherent fabric. To overcome the performance loss induced by the higher latency of CXL, tiering systems keep hot data in DRAM and demote cold data to the slower tiers. While most research has focused on the...

Sujay Yadalam, Saarth Deshpande, Divyanshu Saxena et al. · Proceedings of the 4th Works... · 0 citations

#artificial intelligence Preprint Dec 2025

Vulcan: Instance-specialized, Verifiable Systems Heuristics Through LLM-driven Search

Vulcan is proposed, a framework that identifies LLM-friendly interfaces that isolate core decision logic from the rest of the implementation and demonstrates up to 4.9% higher savings for spot-VM scheduling, up to 2% lower miss ratios for cache eviction, and up to 14% higher application performance for tiered-memory sy...

Rohit Dwivedula, Divyanshu Saxena, Sujay Yadalam et al. · 1 citation