UpDown: Efficient Manycore based on Many Threading and Scalable Memory Parallelism
Manycore architectures are a promising direction for single-chip performance. They typically use in-order cores and caches as building blocks and can produce good performance on regular applications. However, on irregular applications, they have low core utilization due to data-dependent control-flow and memory access. We propose UpDown manycore that employs a novel core with Event-Driven Scheduling (EDS), Software-controlled Lightweight Threading (SLT), and Split-transaction Memory Access with software synchronization (SMA) to deliver both high core utilization and chip performance. On a variety of graph and sparse applications, UpDown outperforms a much larger commercial multicore chip (20-core, OoO) by up to 81x. Compared to simple, in-order cores, the UpDown core’s novel mechanisms provide a 2.4-5.9x performance advantage, specifically 1.9x (EDS), 1.4x (SLT), and 1.4x (SMA). For a manycore chip, these architectural benefits enable a 2048-core UpDown to outperform an 8192-core in-order chip of similar Si area by 3.1x overall. By efficiently scheduling computation from many parallel threads, UpDown achieves high core utilization. Further, UpDown mechanisms enable it to more effectively exploit the growing bandwidth available from HBMs and tolerate higher NoC latencies, supporting future scaling. Finally, we also show that UpDown achieves better performance than a state-of-the-art GPU normalized by area.