Machine Learning-Assisted Optimization of CMOS VLSI Circuits for Low-Power and High-Speed Applications
Scaling of complementary metal-oxide-semiconductor (CMOS) technology into the deep-nanometre regime has made the simultaneous minimisation of power and propagation delay one of the hardest problems in very-large-scale integration (VLSI) design. Supply voltage, threshold-voltage assignment, transistor sizing, body biasi...