This work proposes SpecLens, an automated framework for LLM-based Verilog generation that derives specification-driven constraints by analyzing behavioral divergence among multiple candidate implementations, using the original specification as the only external semantic source during generation.
DiffLUT-Net is presented, an FPGA-native network connected by six-input LUTs that are trained from scratch, demonstrating the effectiveness of jointly learning LUT functions and sparse connectivity for compact FPGA-native inference.
Jian-Qing Ye, Xin-Rui Gong, Jing-Cun Wang et al.· 0 citations
The first systematic study of imperfect specifications is presented and an automated framework to repair them to enhance the quality of resulting Verilog design is proposed, demonstrating the capabilities of specification repair by {VClare} as well as further potential of LLMs in front-end hardware design.
Zhuorui Zhao, Bing Li, Yu Li et al.· arXiv.org· 0 citations
This paper discusses the evolution of EDA from localized assistance to autonomous agentic execution, and reviews representative advances of LLMs in front-end design, focusing on key tasks such as circuit and testbench generation from a shared specification.
