Open access
Aug 2026
Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
This work presents a configurable hardware intellectual property (IP), non-intrusive in fault-free operation, that detects AXI4 protocol violations and timing faults at runtime and restores interconnect liveness through a cut-and- drain isolation mechanism.
Chao-Qun Liang, Thomas Emanuel Benz, A. Ottaviano et al.
· IEEE Transactions on Very La... · 0 citations