A High-Throughput, Low-Power SRAM-Based Spiking Neuron Network Accelerator
Spiking Neural Networks (SNNs) are promising for low-power edge intelligence due to their event-driven computational model. However, their hardware implementation poses challenges in terms of energy efficiency and memory access overhead. This paper presents an SRAM-based near-memory computing neuromorphic core supporting 256 leaky integrateand-fire neurons and 65,536 synapses. Synthesized in 40 nm low-power CMOS, the core occupies 0.3 mm2, operates at 70 MHz, consumes 7.67 mW, and achieves $\mathbf{0 . 6 4} \mu \mathbf{J}$ per inference and 0.22 pJ per synaptic operation. A five-core SNN system reaches 96% accuracy and 11 kFPS throughput on the MNIST dataset. A complete System-on-Chip was fabricated using SkyWater 130 nm CMOS via the eFabless multi-project wafer platform, including a small programmable computing core interfaced with a RISC-V processor via the Wishbone bus as a standard memory-mapped peripheral. This core implements 32 neurons and 8,192 synapses, and occupies 0.33 mm2 within a total chip area of 7 mm2. Firmware was loaded onto the SoC to verify the functionality of the full hardware-software system. Measurement results confirm improved energy efficiency and real-time performance, highlighting the suitability of SRAM-based architectures for ultra-low-power neuromorphic computing at the edge.