DDRop: Active Memory Interposer Attacks on Confidential VMs by Dropping DDR5 Writes
ETHZurich, Zúrich, Switzerland et al.
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Open access
Aug 2026
User Privacy Attacks through Self-Modifying Code Conflicts
This paper systematically analyze a set of x86 instructions that directly or indirectly invalidate instruction cache lines, revealing measurable timing asymmetries between cache hits and misses, and shows that these SMC-induced timing artifacts can be leveraged to mount high-resolution cache attacks that are both steal...
Seonghun Son, Daniel Moghimi, Berk Gulmezoglu
· ACM Transactions on Architec... · 0 citations