Open access
Aug 2026
A Memory-Efficient Depthwise Separable Convolution Accelerator Using Run-Length Coding
A memory-efficient hardware accelerator for depthwise separable convolution that minimizes off-chip memory traffic and parameter storage and performs the depthwise separable convolution with a small number of logic resources and on-chip memory, confirming its feasibility for resource-constrained edge devices.
Jaeseong Kim, Taehong Min, Chaebin Lee et al.
· Electronics · 0 citations