Open access
Jul 2026
RISC-V-based YOLOv3-tiny acceleration with runtime-reconfigurable systolic arrays and custom instructions.
A RISC-V-based acceleration framework for YOLOv3-tiny inference that combines a tightly coupled CPU-accelerator architecture with runtime-reconfigurable hardware support and demonstrates the effectiveness of the proposed processor-coupled acceleration architecture for YOLOv3-tiny-based detection inference on edge platf...
Shuya Wang, Xue-Cong Chen, Detao Nie et al.
· Scientific Reports · 0 citations