Durgam Muskinamma, Gutti Nagaswetha

Low Power and High-Speed VLSI Architecture for AES Cryptographic Processor

This paper shows that a single architecture can be used to build fast and ultra-low-power AES hardware efficiently on FPGA, ASIC, and RISC-V. The system uses automated design exploration and adaptive decision-making to choose architectural parameters like pipeline stages, S-Box implementation, and voltage-frequency sca...