Real-time FPGA-Driven Structural Health Monitoring of Composite Structures Using Machine Learning-based Methods
The safety and integrity of composite structures can be ensured by real-time detection of damages such as impact events or delamination. Real-time Structural Health Monitoring (SHM) systems help to achieve immediate damage detection, localization, and even quantification with a fast response time. At the same time, the acquisition of damage-sensitive indicators from multiple onboard sensors generates vast amounts of data, imposing high computational resources. This requires the development of low-power embedded systems capable of performing high-speed and efficient data processing. Field-Programmable Gate Array (FPGA)-based systems address these challenges by offering parallel processing capabilities, flexibility, high-speed multi-I/O interfaces, and low power consumption. Machine learning algorithms aid SHM by processing extensive datasets to automatically extract damage-sensitive features, enabling the analysis and detection of damage. The proposed system utilizes Ultrasonic Guided Waves (UGWs) to detect damage-sensitive features in composite structures. Piezoelectric transducers (PZTs), attached permanently to the structures, are used to transmit and receive UGWs, that exhibit feature changes when damage is present. Pre-processing data using various signal processing techniques is carried out with integrated electronic embedded devices after data acquisition. As the primary objective of the system is real-time monitoring using FPGA, the machine learning model was trained with synthetic data, under simulated damage conditions, considering hardware resource requirements. The model, reconstructed using trained parameters in FPGA, was evaluated for latency performance. This paper presents a real-time SHM system that combines the capabilities of FPGA and machine learning to evaluate the durability and integrity of composite structures. The developed ML model achieved over 95\% accuracy in classifying damages and estimated damage sizes with a standard deviation less than 2 mm. Implementing an application on an FPGA using traditional design methods (Hardware Description Languages, HDLs) demands substantial learning and significant development time. To address these challenges, a framework known as High Level Synthesis (HLS) was employed to develop an FPGA system, enabling the hardware behavior to be described using high-level programming languages such as C or C++, thereby accelerating the learning curve. A range of optimization techniques using HLS was applied, resulting in parallel execution and reduced latency. Overall, this system offers a robust and rapid solution for real-time SHM, thereby contributing to condition-based maintenance and damage escalation prevention.