System-Level Processing-Time Analysis of a NodeMCU-Based Asynchronous JK Flip-Flop Chain
This study experimentally evaluates system-level processing and response times in a NodeMCU (ESP8266)-based software implementation of an asynchronous JK flip-flop (JK/FF) chain. Unlike field-programmable gate array (FPGA)-based remote-laboratory or hardware-level propagation-delay studies, the work focuses on timing o...