Author

Gregg Baeckler

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Preprint Oct 2026

Minimum RISC-V: Maximum FPGA Efficiency

RISC-V processors are now widely available for FPGAs, with most FPGA vendors replacing their proprietary soft-CPU architectures with this instruction-set architecture (ISA). Although contemporary FPGAs are increasingly resource- and feature-rich, a soft processor system---including memory---often occupies a disproporti...

Martin Langhammer, Bogdan Pasca, Gregg Baeckler · 0 citations