POSTER: VibeNIC: Toward LLM-driven Agile Development of FPGA SmartNICs
FPGA SmartNICs combine wire-speed performance with full datapath customizability, yet remain among the hardest to program. LLM coding agents ease development but stumble on system-scale FPGA design: physical overhead and long toolchain runtime, far from the network function, degrade convergence and design quality across the agentic loop. While agentic development tolerates higher intrinsic complexity, a framework must eliminate the incidental complexity of FPGA design-space exploration. VibeNIC is a SmartNIC framework co-designed at every layer for an LLM developer. Its shell absorbs board-level complexity into a timing-closed base NIC behind standard interfaces, shrinking each iteration to a user-partition-only recompile and leaving most design space reconfigurable. A building-block library atop it lets the agent compose rather than microarchitect, grounded by documentation, examples, and prompts (DEPs) in shell and library contracts. A case study on a stateful HBM-augmented UDP datapath delivers a working end-to-end design in hours.