Jie Han

PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics such as the worst negative slack...

HAP: Efficient Quantization Harnessing Adaptive Precision for DNN Hardware Acceleration

CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models

CoEvoP&R addresses limitations with a large language model (LLM)-based framework that automatically evolves analytical placement objectives and reduces post-route routed wirelength and congestion across eight ChiP-Bench Nangate45 designs and three seeds.