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Author

Joseph Maheshe

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Conference Sep 2026

CIA: Composable Instruction-Based Accelerators

The use of custom instructions is a common approach to accelerate domain-specific problems. However, it is difficult to reuse instruction-based accelerators in new systems — for example, if multiple accelerators from past systems are merged into a single SoC, they may have colliding opcodes. Fixing this requires opcode...

Brandon Freiberger, Joseph Maheshe, J. Gray et al. · 0 citations
Conference Sep 2026

Shared Load-Store Unit for Instruction-Based Accelerators

Modern systems-on-chip (SoCs) rely on heterogeneous accelerators for performance scaling. Memory access is a critical bottleneck, but the complexity of cache coherence and nuances of weak memory consistency models (which may vary from system to system) represent a significant designer burden to every load/store unit th...

Joseph Maheshe, G. Lemieux · 3 citations

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