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PACT is presented, a Post-route Agentic Checkpoint Tuning framework for Vivado design checkpoints (DCP), which represents post-route tuning as validation-gated transitions between accepted and candidate checkpoints.
EDA flow parameter tuning is critical for quality-of-results~(QoR), yet the parameter space is large, tightly coupled, and full evaluations are prohibitively expensive. Prior LLM-assisted tuners mainly use the LLM as an external proposer with transient working context; we instead present \textbf{StateTune}, which refor...
Field-programmable gate arrays (FPGAs) have been an efficient alternative of implementation for digital circuits. Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the LUT input number to improve performance and logic capacity will introduce exponential area ove...
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