Wafer-scale accelerators offer a new scaling point for AI infrastructure, but they also create a new compilation regime: communication cost varies sharply with location, and the space of possible placements and execution schedules is enormous. Existing GPU, distributed, and vendor compilation systems largely retain a s...
Ye-Qi Huang, Cong-Jie He, Hao-Cheng Xiao et al.· Proceedings of the ACM SIGOP...· 0 citations
This work presents TileSight, a tile-centric performance-modeling tool that elevates the tile from a programming primitive to an analysis primitive, and selects tile configurations competitive with strong vendor and expert baselines.
Zhiwen Mo, Yu Cheng, Lei Wang et al.· arXiv.org· 1 citation
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