Open access
Jul 2026
HiKV: Hierarchical Importance-Aware KV Cache With Hardware Acceleration for LLM Decoding
HiKV is a novel algorithm-hardware co-design that exploits KV cache redundancy through hierarchical importance awareness and outperforms state-of-the-art importance-based methods by achieving an additional 1.87x reduction in external memory accesses.
Chao Fang, Jun Yin, Man Shi et al.
· IEEE Transactions on Circuit... · 0 citations