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Manjunath G. Asuti

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Aug 2026

IoT-Based Smart Flood Monitoring and Early Warning System

Floods pose a significant hazard in India, causing severe damage to life, property, and the economy. Existing flood monitoring systems often suffer from delayed response, limited coverage, and high costs. The objective of this study is to design and implement a low-cost, real-time IoT-based smart flood monitoring and early warning system that can improve prediction accuracy and provide timely alerts to minimize flood impacts The proposed system integrates multiple sensors-ultrasonic for water level, water flow sensors, and DHT22 for temperature and humidity-with an Arduino Uno microcontroller. Data is transmitted to the ThingSpeak cloud platform using the ESP8266 Wi-Fi module and visualized via the ThingView mobile application. A GSM module sends SMS alerts to authorities and residents when threshold conditions are detected. The system was simulated using Proteus Professional to verify performance, and individual modules were tested for accuracy and responsiveness. The proposed system overcomes limitations of traditional flood monitoring approaches by enabling automated, continuous, and low-cost sensing with cloud-based data access. Multisensor integration reduces false alarms compared to single-parameter systems. While the Wi-Fi + GSM approach provides effective coverage for urban and semi-urban areas, rural deployments may require extended-range communication protocols. Security enhancements and machine learning integration are recommended for predictive analytics and robust performance in div This IoT-based flood monitoring and early warning system provides a scalable, affordable, and effective solution for real-time flood risk management. By integrating multiple environmental parameters, cloud storage, and multi-channel alerts, it significantly improves upon existing methods. The architecture offers a strong foundation for future enhancements, including AIdriven prediction models and secure data transmission protocols, to further strengthen disaster preparedness and response.

N. Benni, S. S, A. G. et al. · 0 citations
Conference Jul 2026

Design and Implementation of a Low-Power 16-Bit MAC Unit using CEBEC SQRT CSLA

Multiply-Accumulate (MAC) units are fundamental hardware blocks in Digital Signal Processing (DSP) systems, where dynamic power efficiency is a critical design constraint. Traditional high-speed MAC architectures frequently employ Square Root Carry Select Adders (SQRT CSLA) for the accumulation stage. However, regular SQRT CSLAs rely on redundant Ripple Carry Adders (RCAs) to compute parallel potential sums for both $\mathbf{C}_{\mathbf{i n}}=\mathbf{0}$ and $\mathbf{C}_{\mathbf{i n}}=\mathbf{1}$ conditions, leading to excessive dynamic switching activity. This paper proposes a highly power-efficient 16-bit MAC architecture utilizing a Carry Enable Binary to Excess-1 Converter (CEBEC) SQRT CSLA. The proposed design entirely eliminates the redundant $\mathbf{C}_{\text {in }} \boldsymbol{=} \mathbf{1}$ RCA blocks, replacing them with a streamlined combinational logic path. This path utilizes optimized NOT and XOR gates for lower-order bits, coupled with targeted OR-gate logic at the Most Significant Bit (MSB) for rapid carry evaluation. The baseline and proposed architectures were functionally verified via Cadence SimVision and synthesized to the gate level using the Cadence Genus Synthesis Solution. Post-synthesis power and area analysis demonstrates that the proposed CEBEC-based MAC unit achieves a significant 36.7% reduction in dynamic switching power compared to the baseline CSLA, dropping from 15.22 $\boldsymbol{\mu} \mathbf{W}$ to $\mathbf{9. 6 3} \boldsymbol{\mu} \mathbf{W}$. While this hardware optimization trades a marginal 5.3% increase in total standard cell area, the substantial mitigation of switching activity makes the proposed architecture highly viable for low-power DSP ASICs.

Shriparna Praveenkumar Hegde, V. D, Manjunath G. Asuti et al. · 0 citations