Author

Minchan Gil

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Preprint Jul 2026

Analyzing RV32/RV64 Trade-offs for FreeRTOS Latency on 8-Stage RISC-V Soft Processors

The design and evaluation of FreeRTOS on custom 8-stage RV32/RV64 RISC-V soft processors with machine-mode CSRs, a CLINT timer, trap and exception control logic, and the required context-switch path are presented.

Hyun-Inn Kang, Geonwoo Yu, Jongwon Kim et al. · 0 citations