Author

Minyi Guo

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Preprint Sep 2026

Shared Phase Arithmetic for Parallel Quantum Rotations

A layer of diagonal quantum gates can be specified by an integer-valued function on computational basis states. This description suggests implementing the layer by evaluating that function reversibly and translating its value into a phase using a shared quantum register. We develop this viewpoint for parallel phase kic...

An-Bang Wu, Li-Qiang Lu, Pu Pang et al. · 0 citations

Preprint Aug 2026

Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference

Deltoris is presented, an algorithm-hardware co-design framework for efficient diffusion-based VLA inference that exploits the temporal similarity of consecutive inputs and proposes a temporal-aware bit-sparsity algorithm that computes only the differences between consecutive inputs, eliminating redundant bit-level ope...

Zheng Liu, Zeyu Guo, Zi-Han Liu et al. · 1 citation

Preprint Sep 2026

Atlas: Algorithm-Hardware Co-Design for On-Device City-Scale 3D Gaussian Splatting in VR

Atlas is presented, an on device city scale 3DGS rendering framework that enables scalable rendering without runtime Internet access and proposes temporal aware LoD search and stereo rasterization to avoid redundant computation in VR.

He Zhu, Zheng Liu, Xingyang Li et al. · 0 citations

Jul 2026

Kaleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by Exploiting Latent Space Correlations

Kaleido is presented, an algorithm hardware codesign that accelerates all operations in vDiTs by exploiting channel-wise spatiotemporal correlations in latent space and skips redundant computations by reusing partial results while preserving higher generative quality than prior methods.

Wen-Xuan Miao, Haosong Liu, Weiming Hu et al. · arXiv.org · 1 citation

Jul 2026

DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction

DSTAR, a software-hardware co-design framework that accelerates DiT inference by reducing spatial and temporal redundancy and incorporates a sparse attention reuse mechanism to minimize redundant computation in attention layers, and design a specialized hardware accelerator which achieves high efficiency in both latenc...

Chi Zhang, Jieru Zhao, Yu Feng et al. · arXiv.org · 2 citations

Preprint Aug 2026

A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation

This work proposes FIBER, a new architecture that extends the GPU SIMT (single instruction, multiple thread) model, and extends the ISA, microarchitecture, and compiler to realize shared-register addressing, conflict-free operand delivery, and fiber-based program mapping.

Zi-Han Liu, Jingwen Leng, Yang-Jie Zhou et al. · 0 citations