Enhancing Scalability and Reliability of 3D ONoCs Through Optimized Routing and Mathematical Modeling
The scalability of multiprocessor networks on-chip is restricted by the performance of on-chip interconnects. Optical networks-on-chip (ONoCs) offer ultra-high bandwidth and energy-efficient solutions for these bottlenecks. Although 2D ONoCs have several advantages, scalability is a challenge because of limited chip area; hence, recently, research has been focused on 3D integration. This paper presents a novel 3D ONoC architecture based on two newly designed routers, the Horizontal Dimension Order Routing Aware Router for intra-layer communication and the Vertical Optical Router for inter-layer connectivity. To evaluate the performance of the routers and the proposed ONoC, comprehensive mathematical models are developed for insertion loss, crosstalk noise, and signal-to-noise ratio (SNR) measurements. The results show that the proposed design reduces average insertion loss by 31.28% and improves worst-case SNR by 9.23% compared with existing 3D ONoC designs. It also outperforms traditional designs in terms of Bit Error Rate (BER). The hybrid switching approach is used for XYZ dimension order routing, enabling high-speed data transmission and avoiding the need for buffering and its latency. Furthermore, the results show that vertical chip expansion improves SNR and BER over horizontal expansion, taking a step toward reliable, high-performance all-optical computing.