Author

Qing Liu

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Open access Sep 2026

A Deterministic FPGA-CPU Data Interaction Architecture with Cache-Aware Core Selection for Real-Time Systems

The architecture introduces two reusable system-level design principles: interrupt-independent notification via sequence counters, avoiding OS-mediated jitter as much as possible, and cache-aware core selection based on the non-uniform cache architecture (NUCA) to reduce the variability of access latency, thereby achie...

Hui-Ji Zheng, Qing Liu, Kang Wang et al. · Electronics · 0 citations