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Conference Aug 2026

A Hardware-Efficient SRAM-Based CNN Accelerator for Edge Image Classification

CNN inference on edge hardware is constrained by memory bandwidth, redundant logic, and the area overhead of fully parallel multiply-accumulate (MAC) units. This paper presents a hardware-efficient CNN accelerator with an SRAM-based architecture optimised for classifying 28×28 grayscale images. Input images are ingeste...

Avinash Krishna Pk, R. S · 0 citations
Conference Aug 2026

Low-Power Binary Neural Network Accelerator with Scalable Processing and Bit-Stream Input

This paper presents the design, simulation, and ASIC-focused implementation of a Binary Convolutional Neural Network (BCNN) tailored for energy-efficient edge AI applications. The proposed architecture utilizes binarized weights and activations, substituting standard multipliers with XNOR-popcount operations to reduce...

Aryan Kodan, R. S · 0 citations

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