Preprint
Jul 2026
Benchmarking LLMs for Verilog Design Flows
A reproducible benchmarking platform that evaluates open-source LLMs on Verilog RTL generation across 50 curated tasks consisting of combinational, sequential, finite state machine (FSM), and mixed designs, enabling reproducible evaluation of generative AI for hardware design workflows.
Angshuman Chakravertty, Rahul Koshti, Buddhi Prakash Sharma et al.
· 0 citations