Author

Reza Ansari

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Preprint Aug 2026

A Time-Multiplexed Spiking Neural Network Accelerator with Pipelined Readout for FPGA Inference

The design and Field-Programmable Gate Array (FPGA) implementation of an inference-only SNN accelerator optimized for MNIST digit classification is presented and it is demonstrated that the proposed microarchitecture provides a resource-efficient solution for real-time neuromorphic edge inference.

Reza Ansari, Maciej Wielgosz · 0 citations