Author

Safiullah Khan

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Jul 2026

PIP-NTT: Towards a Scalable Memory-Parallelized Accelerator for Iterative NTT in PQC

This work proposes a memory-parallelization strategy using four smaller n/4-sized memories for ring size n, preserving the total memory footprint of conventional designs and introduces a multiplication-free rescaling architecture for the inverse NTT.

Malik Imran, A. Khalid, C. Rafferty et al. · arXiv.org · 0 citations