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Author

Swati Mishra

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Open access Sep 2026

Novel Microarchitectural Side-Channel Attacks on Open-Source RISC-V Cores

We present a simulation-to-silicon security characterization of microarchitectural side channels on open-source RISC-V cores. Twenty-three attack classes are measured across a six-core corpus that spans the design space from simple in-order pipelines (Rocket, VexiiRiscv) through a single-issue in-order core (CVA6) to a...

Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra et al. · 0 citations
Open access Aug 2026

PACE: A Page-Adaptive, Cache-Anchored Memory Encryption Engine for RISC-V with Formally Verified nth-Order DPA Resistance

PACE is presented, a page-adaptive, cache-anchored memory encryption engine for RISC-V that makes nth-order DPA resistance practical and keeps cryptographic latency off the cache eviction critical path and demonstrates side-channel-hardened memory encryption on open RISC-V hardware.

Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra et al. · 0 citations

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