Author

Tian-Yu Jia

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Preprint Sep 2026

VSpector: Specification-Driven Bug Detection for RISC-V CPUs

VSpector is presented, a specification-driven bug detection pipeline that directly checks whether CPU register-transfer level (RTL) implementations adhere to official specification rules, without requiring specialized construction of reference models, formal properties, or custom bug patterns.

Tian-Yu Jia, Zhao-Yang Yu, Yuan-Liang Chen et al. · 0 citations