Erasure coding provides efficient fault tolerance for large-scale distributed storage systems. However, its data repair process is well-known to be resource-intensive. We find that conventional host-centric, TCP-based repair architectures suffer from severe resource contention. Even in high-bandwidth networks, such interference slows repair operations and degrades service quality. To address this limitation, we propose DPUEC, a novel architecture that fully offloads the entire repair process to a Data Processing Unit (DPU). DPUEC leverages Remote Direct Memory Access (RDMA) to enable kernel-bypass data transfers and utilizes the onboard multi-core processors of DPU for highly parallel decoding. This design establishes a physically isolated data plane for repair traffic, completely bypassing host resources. Our prototype evaluation shows that DPUEC improves repair throughput by 133% - 181% over the state-of-the-art approach across different workloads. More importantly, DPUEC delivers true performance isolation. It eliminates any interference with foreground applications and reduces host CPU utilization on the recovery node to nearly zero.
Hybrid flash storage combines large-capacity highdensity flash memory with high-performance low-density flash memory, providing excellent cost-effectiveness. Existing data placement strategies for hybrid flash storage typically employ hotness-based data migration relying on a twotier architecture. This approach not only overlooks the variations in read retry counts across different reliability stages, but also leads to severe capacity degradation and exacerbated write amplification. To address these issues, we propose RARO, a Reliability-Aware Read performance Optimization scheme for hybrid flash storage. RARO redesigns data placement by leveraging application-level data access patterns and device-level flash reliability. This is achieved by dynamically migrating data based on its retry count and access hotness. Data residing in an unsuitable flash type triggers immediate migration, with higher priority given to data exhibiting both high retry counts and hotness for placement into low-density flash, thereby enabling proactive performance optimization. Furthermore, RARO employs a progressive threetier (SLC-TLC-QLC) management framework to mitigating the capacity loss. The evaluation of RARO, conducted on the FEMUbased emulator, significantly enhances read performance, with IOPS reaching 9.46× to 15.9× of the baseline across different aging stages, while also recovering 57% to 92% of the usable device capacity.
Han Yan, Dingcui Yu, Yanyun Wang et al.· IEEE Non-Volatile Memory Sys...· 0 citations
