Temporal predictability in real-time preemptive embedded systems is strongly influenced by how execution contexts are interrupted and resumed. This paper investigates whether hardware-assisted context preservation can reduce the temporal jitter introduced by conventional task switching in a RISC-V real-time execution model. A controlled comparative evaluation is performed between a standard shared-pipeline execution configuration and a context-preserving multi-context execution configuration under identical scheduler-driven periodic workloads. The study focuses on determinism-oriented task switching indicators, including deadline misses, preemption counts, switch-related flush events, and accumulated switch overhead. Four control-oriented experimental scenarios are used to expose progressively different switching conditions, ranging from baseline periodic execution to frequent preemption, near-saturation behavior, and tight-deadline pressure. The results show that preserving execution context across preemptions consistently reduces switching overhead and improves deadline-related behavior under recurring real-time activations. The benefits of context-preserving execution become progressively more visible under elevated preemption pressure, reduced timing slack, and tighter deadline conditions. The study therefore provides a controlled comparative basis for analyzing deterministic task switching in RISC-V real-time execution models.
Nicolai Iuga, I. Zagan, N. Găitan et al.· International Conference on...· 0 citations
As RISC-V processors are increasingly considered for embedded real-time and control-oriented systems, evaluating how timing behavior changes under increasing task concurrency becomes essential. Adding runnable tasks can amplify preemptions, context-switch activity, response-time variability, execution jitter, and deadline pressure. Existing RISC-V simulation and virtual-platform environments mainly target architectural exploration, functional validation, or full-system execution, and do not directly provide a controlled workflow for isolating scheduler-induced timing degradation across large configuration spaces. This paper presents nSim-RV, a configurable and reproducible RISC-V simulation and orchestration framework for scheduler-aware timing scalability evaluation. The framework combines automated campaign generation, deterministic workload configuration, structured dataset aggregation, duplicate validation, and timing-oriented metric extraction. The evaluation compares a standard shared-pipeline execution model with an nMPRA-inspired preserved-context mode under identical scheduler and workload conditions. The campaign includes CoreMark, Dhrystone, and a deterministic synthetic RT-Control workload, 2–32 concurrent tasks, 50 k–1 M cycle observation windows, cache-disabled and cache-enabled configurations, and four-stage and five-stage pipeline organizations, resulting in 864 validated configurations. Results show that increasing task concurrency amplifies timing variability and deadline pressure. Preserved-context execution reduces switching-induced disturbance and delays or reduces higher-pressure timing behavior in several trajectories. Under the five-stage cache-disabled RT-Control configuration at N = 32, it reduces the deadline miss ratio from 3.74% to 2.21%, corresponding to a 41.1% relative reduction, with the clearest benefits observed for Dhrystone and RT-Control at intermediate–high task counts.
Nicolai Iuga, N. Găitan, I. Zagan et al.· Computers· 0 citations