Author

X. S. Hu

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Preprint Aug 2026

VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration

VIPER is presented, a unified, lightweight, and architecture-aware performance evaluation framework for PIM DSE, providing rapid architecture-aware performance estimates for iterative DSE without repeated cycle-accurate simulation.

Hao-Ran Geng, T. Pereira, Xiaoyang Lu et al. · 0 citations

Book Open access Aug 2026

Codebook-Based Acceleration for Ternary Language Model Inference

TERINT-GEMV is designed, a multiplier-free bit-serial accelerator that ingests the 6-bit indices directly through an on-chip lookup table, computing ternary × INT8 dot products with dynamic zero-skipping.

Tomas Sousa Pereira, Ruibao Wang, Ikenna Nwozo et al. · International Symposium on L... · 0 citations