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Author

Xilai Dai

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Sep 2026

FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage

This work proposes Double-Duty, a logic block architecture that decouples LUTs and adder chains by augmenting four extra inputs of the logic element to bypass LUTs and directly drive the adders.

Xilai Dai, Junius Pun, Anthony Fei et al. · 0 citations

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