Y. Wong

A 10-bit Synchronous SAR ADC with Dynamic Clock Phase Generation for Ultra-Low Power Mixed-Signal Applications in 45nm CMOS

The increasing demand for energy-efficient and high-performance analog-to-digital converters (ADCs) in modern wireless communication systems necessitates the development of architectures that balance speed, accuracy, and power consumption. This work addresses the challenge by designing and verifying a synchronous Succe...