MAFlow: A Memory-access Optimized CNN Inference Dataflow for Large-sized Feature
Due to the limited memory bandwidth of embedded systems, Convolutional Neural Networks (CNNs) often suffer from slow inference speeds when processing large-sized feature maps. This paper proposes a dataflow design named MAFlow, which includes the design of a hardware architecture and a five-step on-chip convolution pipeline. By eliminating repetitive off-chip data requests and greatly reducing memory suspension during convolution operations, MAFlow significantly enhances memory bandwidth utilization and reduces convolution latency. In the simulation for the convolution layers in AlexNet, MAFlow achieves a 16.5% reduction in DRAM access and a 72.6% reduction in latency at the cost of 1.69 MB of additional on-chip storage overhead. In the simulation for convolution operation with 2000×2000 input feature map, MAFlow maintains the DRAM bandwidth utilization rate above 84% and achieves a latency of 62.4 ms.These results highlight MAFlow's effectiveness in accelerating CNN inference for large-sized feature in memory-intensive applications.