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CIMERA is presented, a reconfigurable-precision LLM inference accelerator that integrates compute-in-interconnect and memory to mitigate the memory wall and enable precision-aware execution.
A hardware-software co-design framework that unifies distributed compute, memory, and communication into a seamless processing-communication fabric is presented and a prefill-decode disaggregation approach that dynamically reconfigures PE organizations to maximize resource utilization is presented.
Evaluation using cycle-accurate hardware-software co-simulation demonstrates that CHIPSMORE effectively sustains high throughput across varying model sizes, context lengths, and batch sizes while maintaining favorable power scaling.
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