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Zeyuan Hou

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Open access Aug 2026

A Schematic-Level Digital Near-Memory Computing Architecture Utilizing 1T3R Memristor Arrays and Pipelined MAC for Pattern Recognition

This work presents a schematic-level digital near-memory computing architecture based on a 1-Transistor-3-Resistor (1T3R) bit-slicing scheme for 3-bit signed weight storage and indicates that the proposed architecture can maintain functional classification capability under 3-bit weight and 2-bit input constraints.

Zeyuan Hou, Xiao-Meng Wang, Yang Yi · 0 citations

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