The SECDA Design Suite is proposed, a set of specialized tools that enable an efficient design process for developing AI accelerators for edge inference, utilizing the SECDA design methodology, and provides a fully integrated environment that allows developers to design, deploy and evaluate new hardware architectures using FPGAs.
A novel open-source framework named OSCAR is proposed, which, given a set of hardware and workload specifications, provides architecture-level power estimation and can also automatically generate Chisel and synthesizable RTL of the custom AI chip.
J. Mok, Qi-Jun Zhang, Di Pang et al.· ACM Transactions on Design A...· 0 citations
Edge inference on resource-constrained embedded nodes demands accelerators that are energy-efficient and compact. This paper presents Versat-AI, an open-source compiler that accepts a standard Open Neural Network Exchange (ONNX) model and generates a complete, synthesisable RISC-V System-on-Chip (SoC) with an embedded...
R. Teixeira, J. Rodrigues, Jaime Aguiar et al.· Journal of Low Power Electro...· 0 citations
Deep Neural Networks (DNNs) are critical to modern AI applications, yet their deployment on standard CPUs and GPUs is constrained by high power consumption and computational latency, particularly in resource-constrained edge environments. To address these limitations, this paper presents the design and implementation o...
P. V. G. K. Rao, Dudekula Raziya· 2026 International Conferenc...· 0 citations
A systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA) is presented, highlighting that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch...
Shuo Wang, Lei Chen, Chunsheng Tian et al.· Electronics· 0 citations
The Compatibility Ratio (CR) is introduced as a simple guideline for evaluating performance trade-offs between optimal hardware micro-architecture configurations across different workloads and shows that, for the considered accelerator, a DNN model-family optimized configuration might occupy an effective middle ground...
Lukas Groth, Andrija Nešković, Rainer Buchty et al.· ACM Transactions on Embedded...· 0 citations
FSGen is proposed, an agile framework for attention-based LLM accelerator generation with an early-stage PPA estimator that supports fused operator dataflows and sparsity with a diverse design space and finds designs with 1.4x better power efficiency or 10x speedup with similar PPA metrics compared to prior work.
J. Mok, Qi-Jun Zhang, Zhi-Yao Xie· 0 citations
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