Jul 2026· 2026 IEEE 10th International Test Conference India (ITC India)· pp. 1-6· 0 citations· 10 references
Abstract
Shift-left DFT methodologies enable early insertion of test logic at the RTL stage, but conventional flows rely on DFT EDA tools to directly insert CODECs, TDRs, MBIST, scan routers, pin multiplexing, boundary scan, and TAP controllers into design RTL, enforcing serial workflows between design and DFT teams, resulting in high tool runtime, license usage, and intrusive design RTL modifications. This paper presents a discrete RTL DFT flow enabling true parallel development at two levels: design-DFT team independence and concurrent wrapper development. Using script-based, modular grey-box abstractions-TestWrap, MemWrap, and IPWrap-the approach decouples DFT integration from functional RTL and continuous tool invocation. A reusable multi-vendor codec library further reduces tool dependency across partitions and projects. Industrial validation across 50 measured design releases demonstrates an average DFT integration turnaround of 3 days, with a worst-case peak of 11 days, while maintaining functional correctness and achieving scalable, cost-efficient shift-left DFT integration in a representative internal deployment.
This paper presents LithOS Bare-Metal (LithOS-BM), a Real-Time Operating System (RTOS) partially compliant with the ARINC 653 APEX standard, designed for small embedded systems where partitioning or virtualization is unnecessary or infeasible, and rapid response times are critical.Integrated Modular Avionics consolidat...
Miguel Gotor-Ramos, Carlos Cuesta-Martínez, Miguel Masmano-Tello et al.· Jornadas de Automática· 0 citations
Large language models (LLMs) can generate register-transfer-level (RTL) code from natural-language specifications, but compilation alone does not establish structural completeness, functional correctness, or implementation efficiency. This paper presents a framework for evaluating LLM-generated RTL beyond compilation,...
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VibeNIC is a SmartNIC framework co-designed at every layer for an LLM developer, and a case study on a stateful HBM-augmented UDP datapath delivers a working end-to-end design in hours.
Yunfan Li, Jialin Li· Conference on Applications,...· 0 citations
RTL source-level debugging research requires benchmark artifacts that provide faulty designs together with precise change locations, executable test stimuli, and reproducible configurations. Available Verilog resources usually provide only a subset of these elements. We present VeriBugBench, a framework for constructin...
Xiankai Meng, Ke-Jian Feng, Xin-Lin Zhao et al.· 1 citation
Conventional undergraduate computer architecture curricula typically prioritize microarchitectural theory validated solely through logic simulation, often omitting the complex engineering layers required for physical hardware deployment and high-level language execution. This work addresses this disparity by presenting...
Pedro Pereira Cecilio Ventura, Lucas Fernando de Souza Lima, Ilana Chaia Finger et al.· Journal of Integrated Circui...· 0 citations
We present an LLM-driven, datasheet-aware framework for early-stage hardware compatibility verification that identifies documentation-level interface incompatibilities based on hardware datasheets and high-level component connectivity descriptions. It does not require, and can therefore be used, before detailed schemat...
Hao-Ran Qiao, Robert P. Dick· 2 citations
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