From NISQ to Fault-Tolerance: Applications and Algorithmic Benchmarks for Spin Qubits
TL;DR
This work shows that the compilation method Parity Twine perfectly complements the hardware's capabilities to perform tasks such as the quantum Fourier transform or QAOA, and describes an error detection technique native to Parity Twine, which EO qubits can leverage in a unique and advantageous way to improve algorithm performance.
Abstract
Motivated by recent breakthroughs in the development of spin-based quantum processing units based on exchange-only (EO) spin qubits, we provide a roadmap for the implementation of quantum algorithms on the EO platform, ranging from the NISQ to the fault-tolerant era. To provide an algorithm-driven perspective on the scaling of quantum chips, we consider a range of applications targeting different stages of hardware maturity and formulate requirements for a successful realization. We show that the compilation method Parity Twine perfectly complements the hardware's capabilities to perform tasks such as the quantum Fourier transform or QAOA. Furthermore, we describe an error detection technique native to Parity Twine, which EO qubits can leverage in a unique and advantageous way to improve algorithm performance. Finally, since both near-term algorithmic benchmarks and a long-term perspective can be found in digital quantum simulation, we specifically discuss the fermionic fast Fourier transform and the simulation of Fermi-Hubbard models. The latter is explicitly discussed in the context of quantum error correction and a partially fault-tolerant realization. By providing detailed resource estimates and identifying scaling bottlenecks on each level, our work offers a quantitative perspective on EO-based quantum computing and will inform future hardware design choices.