Sep 2026· IEEE Internet of Things Journal· Vol 13, pp. 42850-42864· 0 citations· 53 references
Abstract
As edge computing nodes and platform-class devices such as industrial gateways become increasingly prevalent, the x86-64 architecture is widely used in these deployments, making memory-safety protection against vulnerabilities in x86-64 commercial off-the-shelf (COTS) binaries a critical security requirement. However, existing mitigation techniques often rely on source code availability or specific compiler/OS support; furthermore, the protection scope of a single mechanism is typically limited, frequently necessitating the combined deployment of multiple defenses. Such superposition of multiple mechanisms tends to introduce significant runtime overhead and compatibility risks, thereby limiting their practical application in resource-constrained scenarios. To address this, we propose FEATHER, a lightweight, multidimensional memory-space hardening framework for x86-64 COTS binaries, designed to effectively harden COTS binaries without requiring source code support. FEATHER employs a program-aware, cross-layer memory-layout hardening strategy that composes application-level binary rewriting with runtime-library-level glibc hardening, covering the target program’s stack, global offset table (GOT), heap, code segments, and glibc. By jointly reinforcing both the application and its dependencies, it significantly reduces the predictability of the runtime memory space. We systematically evaluate FEATHER in terms of security, file size expansion, and performance overhead using Nginx, Redis, SQLite, and 20 representative Coreutils/Binutils programs, while constructing three representative application scenarios to analyze its applicability under different workloads and attack models. The experimental results show that FEATHER reduces the reliability of the evaluated exploitation paths while incurring modest overhead for most tested workloads. Its performance overhead is comparable to that of commonly used secure-compilation options and secure heap allocators.
Lattice is introduced, a novel RISC-V TEE framework that enables scalable enclaves on commercial RISC-V platforms with a minimal Trusted Computing Base (TCB) and proposes a non-intrusive Secure Monitor design for the underlying firmware.
Yu Zhao, Jia-Bei He, Ming-Ru Xu et al.· ACM Transactions on Architec...· 0 citations
Heterogeneous parallel error detection architecture has been widely studied for safeguarding OoO superscalar processors in safetycritical systems, as it achieves significantly lower hardware overhead compared to traditional LockStep, by exploiting the parallelism that exists in a secondary execution. However, previous...
Ting-Bin Wang, Zhen-Jun Guo, Bing Guo et al.· 0 citations
Co-design of hardware and software offers stronger security and ease of use The CHERIoT platform is a RISC-V-based ISA, an RTOS, and a programmer model that were co-designed for security. The ISA provides hardware mechanisms for enforcing spatial and (heap) temporal memory safety, type safety for opaque types, and ligh...
This paper presents LithOS Bare-Metal (LithOS-BM), a Real-Time Operating System (RTOS) partially compliant with the ARINC 653 APEX standard, designed for small embedded systems where partitioning or virtualization is unnecessary or infeasible, and rapid response times are critical.Integrated Modular Avionics consolidat...
Miguel Gotor-Ramos, Carlos Cuesta-Martínez, Miguel Masmano-Tello et al.· Jornadas de Automática· 0 citations
Memory-corruption errors remain a leading cause of high-impact vulnerabilities in C and C++ software. Deterministic detection, however, remains difficult to deploy: compiler-based sanitizers require source code and control of the build pipeline, hardware-assisted schemes depend on specific platforms, and dynamic binary...
Adel Belkhiri, Michel Dagenais, Maxime Lamothe· 0 citations
Database systems are predominantly developed in unsafe languages (e.g., C/C++) to meet performance requirements through low-level memory management, yet this reliance renders them prone to systemic memory-safety issues that compromise reliability, consistency, security, and durability. Through an extensive bug analysis...
Ilya Meignan-Masson, Martin Fink, Masanori Misono et al.· 0 citations
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