Aug 2026· Proceedings of the ACM SIGCOMM 2026 Conference· 0 citations· 18 references
TL;DR
Evaluation results show that, while these mechanisms consume a small amount of link bandwidth, CBFC can greatly reduce receive buffer utilization, and LLR can substantially mitigate network performance degradation caused by packet corruption.
Abstract
The ever-increasing demand for network performance in large language models promotes the advent of many Scale-up networking schemes. To consistently deliver superior low latency and high bandwidth, these schemes have widely adopted Credit-based Flow Control (CBFC) and Link Layer Retry (LLR) to ensure link-level lossless transmission. However, there is currently a lack of evaluations for these mechanisms in Scale-up domains. This paper builds an FPGA-based Scale-up network to evaluate these lossless mechanisms. Evaluation results show that, while these mechanisms consume a small amount of link bandwidth, CBFC can greatly reduce receive buffer utilization, and LLR can substantially mitigate network performance degradation caused by packet corruption.
Due to the high operational complexity and limited deployment scale of lossless RDMA networks, the community has been exploring efficient RDMA communication over lossy fabrics. State-of-the-art (SOTA) lossy RDMA solutions implement a simplified selective repeat mechanism in RDMA NICs (RNICs) to enhance loss recovery efficiency. However, these solutions still face performance challenges, such as unavoidable ECMP hash collisions and excessive retransmission timeouts (RTOs). In this paper, we enhance RDMA reliability with the goals of being independent of PFC, compatible with packet-level load balancing, free from RTO, and friendly to hardware offloading. To this end, we propose DCP, a transport architecture that co-designs both the switch and RNICs, fully meeting the design goals. At its core, DCP-Switch introduces a simple yet effective lossless control plane, which is leveraged by DCP-RNIC to enhance reliability support for high-speed lossy fabrics, primarily including header-only-based retransmission and bitmap-free packet tracking. We prototype DCP-Switch using P4 switch and DCP-RNIC using FPGA. Extensive experiments demonstrate that DCP achieves $1.6\times $ and $2.1\times $ performance improvements, compared to SOTA lossless and lossy RDMA solutions, respectively.
Wenxue Li, Xiangzhou Liu, Yunxuan Zhang et al.· IEEE Transactions on Network...· 0 citations
Optimizing burst-heavy datacenter workloads necessitates finegrained network control and visibility. We introduce CSIG, a protocol that delivers precise, multi-bit bottleneck congestion signals via a fixed-length Ethernet header. The architecture captures μsgranularity switch metrics, such as available bandwidth, and signals them to end-hosts using in-band, line-rate operations. We propose Fast Ramp-Up, a congestion control primitive that leverages these bottleneck signals to reduce median RPC latency by 20% and unclaimed bandwidth by 60% in production. Beyond transport-level performance, CSIG enables flow-aware observability by embedding μs-scale metrics into every packet, allowing individual application transfers to pinpoint their bottleneck location, such as the topology tier limiting their performance. CSIG thus transforms network telemetry from post-hoc correlation into a real time, context-aware capability. We demonstrate CSIG's broad deployability by validating it across five generations of commodity switch hardware (up to 102.4 Tbps), four NIC generations, and five transport stacks. Our design proves that a streamlined Layer 2 approach, focusing exclusively on the principal path bottleneck, provides transport-agnostic gains without requiring forklift hardware upgrades.
Abhiram Ravi, N. Dukkipati, Weiwu Pang et al.· 0 citations
A closed-loop control architecture is presented that applies an adaptive safety margin to the network estimates, ensuring the system meets a deadline-constrained reliability target, and it is demonstrated that the system converges towards the target loss rate, even under model mismatch, while also quickly adapting to shifts in network conditions.
Moritz Miodek, Marlene Böhmer, T. Herfet· Euromicro Conference on Real...· 0 citations
An experimental evaluation of ALTQ/CBQ demonstrating its sensitivity to a wide range of parameters and link layer driver design issues is attempted and suggestions for effective deployment in real networks are made.
Quanta is presented, a redundancy-aware simulation framework that eliminates repeated execution in packet-level simulation and reduces the dependence of simulation cost on physical network scale.
Jiajun Luan, Hao Li, Yihan Dang et al.· Asia-Pacific Workshop on Net...· 0 citations
Protocols such as L4S for low latency network services have attracted growing interest from major industry stakeholders such as Comcast, Apple, T-Mobile, and NVIDIA. However, L4S requires isolation between L4S flows and classic flows in order to maintain its low latency benefits and safe coexistence. The L4S architecture uses a DualPI2 AQM mechanism to provide this isolation when the bottleneck occurs at the home access link. In practice, however, bottlenecks may also occur at other locations in the network, such as peering points, ingress to wide area networks, or occasionally congested links in the core, where deploying DualPI2 AQM is not feasible. Without a solution to this problem, L4S may struggle to gain deployment, since its benefits may remain limited without end-to-end support. To address this challenge, we propose a deployment strategy that reduces the need to upgrade expensive core routers by using existing networking mechanisms such as BGP communities, SRv6, and priority queues with rate caps. We demonstrate the feasibility of this approach through large scale experiments on the FABRIC testbed. Our results demonstrate a practical deployment strategy for extending low latency service across the Internet, even across independently administered networks.
Harkirat Singh, Fatih Berkay Sarpkaya, Hakan Gulec et al.· 0 citations