Sub-Two-Bit Ternary Weight Storage with Table-Free Arithmetic Decoding for CPU Inference

Abstract

Ternary (1.58-bit) language models are stored in practice at two bits per weight, 26% above the information content of a ternary symbol. The code that removes that redundancy is not new: five ternary values as the base-3 digits of one byte at 1.600 bits per weight is llama.cpp's TQ1_0 and Spectra 1.1's TQ1; the depth-one, table-free decode is used by the NTRU reference implementation; the condition under which a denser format pays is due to Zukowski et al. What this paper offers is measurement. We build t5b, the same construction at a block length of 160 with the scale carried in the existing i2_s per-tensor tail, integrate it into llama.cpp as a distinct ggml type alongside the shipped two-bit format, and measure it end to end on BitNet-b1.58-2B-4T. The re-encoding is lossless: output is bit-identical, and perplexity over 20,480 tokens of WikiText-2 agrees with the two-bit baseline to six significant figures. The checkpoint shrinks from 1.10 GiB to 1.00 GiB, and under llama-bench at four threads the median over five invocations is 1.119x prompt and 1.133x generation throughput, faster in five of five. Against TQ1_0 on the same machine the size margin is 4.7% of the ternary payload. The profitability condition is measured rather than assumed, with both terms taken from the part the kernel runs on; a depth-one decode transplanted into upstream's TQ1_0 kernel does not pay there. We further report that 4.76% of the model's feed-forward neurons are identically zero, in coinciding gate/up index sets in all thirty layers, surviving an independent fine-tune exactly. All results are from one AVX2 host without VNNI; a reviewer's runs on an Intel Xeon reproduce the arithmetic ratio and show it rising by 8.8% under VNNI, at a magnitude smaller than VNNI-targeted systems' eight-bit storage choice would suggest. Changes in version 2 (30 pages; version 1 had 28). No measurement changed. Six corrections resolve places where the text contradicted itself: the abstract called the arithmetic ratio across five microarchitectures stable while Section 8 rejects exactly that; a heading and the conclusion quoted 14%, which is one of five invocations rather than the 13.3% median; the four-thread verdict appeared in three incompatible forms; and the dead-neuron passage referred to a SwiGLU block although the cited technical report states squared ReLU. Added: a three-quantisation comparison on unmodified llama.cpp master, where the SiLU arms agree to 0.14% and the squared-ReLU arms to 0.16%, placing that defect in the compute graph rather than in any quantisation path; and a limitation that was missing before, namely that the third decimal of the microarchitecture table depends on the translation unit rather than the target processor, moving by 0.33%.