An FPGA Integrated Programmable Switch Architecture for Data Plane DNN Inference

Abstract

Machine learning (ML) is increasingly used in network data planes for advanced traffic analysis, but existing solutions (such as FlowLens, N3IC, BoS) still struggle to simultaneously achieve low latency, high throughput, and high accuracy. To address these challenges, we present <inline-formula> <tex-math notation="LaTeX">$\textsf {FENIX}$ </tex-math></inline-formula>, a hybrid in-network ML system that performs feature extraction on programmable switch ASICs and deep neural network inference on FPGAs. <inline-formula> <tex-math notation="LaTeX">$\textsf {FENIX}$ </tex-math></inline-formula> introduces a Data Engine that leverages a probabilistic token bucket algorithm to control the sending rate of feature streams, effectively addressing the throughput gap between programmable switch ASICs and FPGAs. In addition, <inline-formula> <tex-math notation="LaTeX">$\textsf {FENIX}$ </tex-math></inline-formula> designs a Model Engine to enable high-accuracy deep neural network inference in the network, overcoming the difficulty of deploying complex models on resource-constrained switch chips. We implement <inline-formula> <tex-math notation="LaTeX">$\textsf {FENIX}$ </tex-math></inline-formula> on a programmable switch platform that integrates a Tofino ASIC and a ZU19EG FPGA directly, and evaluate it on real-world network traffic datasets. Our results show that <inline-formula> <tex-math notation="LaTeX">$\textsf {FENIX}$ </tex-math></inline-formula> achieves microsecond-level inference latency and multi-terabit throughput with low hardware overhead, and delivers over 90% accuracy on mainstream network traffic classification tasks, outperforming the state of the art.