A Post-Compilation Side-Channel Attack Countermeasure Framework for STM32
Abstract
The prolific deployment of embedded systems across critical infrastructure has made hardware security a pressing concern. For example, inexpensive microcontrollers, such as the STM32 series, are frequently deployed with cryptographic firmware that is vulnerable to Side-Channel Attack (SCA), such as Correlation Power Analysis (CPA). Subsequently, manually implementing existing software-based countermeasures, including random delays and instruction shuffling, can be difficult, tedious, and error-prone. This work presents an automated, toolchain-agnostic framework that secures existing firmware by injecting random jitter and dummy instructions at the assembly level. Furthermore, a software-based AES-128 implementation on an STM32F446RE is utilized to validate the proposed framework through a minimalist power analysis setup. Evaluation indicated that the average Guessing Entropy (GE) increased from 75.9 at baseline to 153.5, rendering key recovery impractical. Moreover, the proposed framework suppressed maximum correlation to noise levels $\left(\rho_{\text {avg }}=0.039\right)$ across all 16 key bytes, resulting in a 0% CPA success rate. In addition, the hardening techniques are lightweight and remain suitable for resource-constrained environments.