FPGA-Based Hardware Accelerator for U-Net: A Resource-Efficient, Pipelined Micro-Architecture for Real-Time Image Segmentation
Abstract
The increasing adoption of modern embedded platforms, edge devices, and AI driven systems has led to higher computational demands. To facilitate that, there should be hardware acceleration techniques capable of delivering higher throughput with minimal latency. Most of the traditional hardware accelerator architectures rely on either High Level Synthesis Tools or utilizing already available Deep Learning Units, which often cost a huge portion of the hardware resources available on a Field Programmable Gate Array. This paper presents a resource efficient pipelined micro architecture optimized for U Net Convolutional Neural Network Architecture for image segmentation, targeting improved resource efficiency while allowing data level parallelism. The proposed design addresses resource efficiency via designing hardware units on Register Transfer Level while using smaller data sizes. Mathematical operations are divided into multiple pipeline stages, which enable the concurrent processing of data streams. This work provides a flexible technique for designing high performance hardware accelerators for real time image processing workloads.