Design of Low Power Advanced Digital Frequency Synthesizer on FPGA

Abstract

Digital Frequency Synthesizers (DFSs) have become an essential component in modern wireless communication, radar, software-defined radio (SDR), instrumentation, and embedded systems due to their capability of generating highly accurate and programmable frequencies. However, conventional synthesizer architectures often suffer from increased power consumption, limited frequency resolution, and higher hardware complexity when implemented on Field Programmable Gate Arrays (FPGAs). This paper presents the design of a low-power advanced digital frequency synthesizer based on the Direct Digital Synthesis (DDS) architecture implemented on FPGA. The proposed architecture employs an optimized Numerically Controlled Oscillator (NCO), phase accumulator, sine lookup table, and clock-enable-based power reduction techniques to minimize dynamic power while maintaining high-frequency accuracy. The design is described in Verilog HDL and implemented using the Xilinx Vivado Design Suite on the Artix-7 FPGA platform. Simulation and synthesis results demonstrate reduced logic utilization, lower dynamic power consumption, and improved timing performance compared with conventional DDS architectures. The proposed synthesizer achieves high frequency resolution with reduced hardware resources, making it suitable for low-power communication and embedded signal processing applications