Cosylab proposes a framework-agnostic abstraction layer that connects AI services to facility control systems without necessarily modifying operational infrastructure, and explores the possibility of using Large Language Model applications as operator copilots and actuating agents, each with distinct safety requirements.
Abstract
A persistent gap separates research-grade Artificial Intelligence (AI) tools from operational accelerator control systems—one that is defined by integration engineering, not model performance. Differences between major control system frameworks—Experimental Physics and Industrial Control System (EPICS), TANGO Controls (TANGO), OPC Unified Architecture (OPC-UA), Distributed Object-Oriented Control System (DOOCS), and Front-End Software Architecture (FESA)—combined with network security constraints, data quality requirements, and operator trust, creates challenges absent from research environments. Cosylab, as an industrial partner within the ARTificial Intelligence For Accelerators, user Communities and associated Technologies (ARTIFACT) network, investigate the possibilities to address this. We propose a framework-agnostic abstraction layer that connects AI services to facility control systems without necessarily modifying operational infrastructure. The architecture enforces safety by default: read-only access, scope-restricted writes, Human-in-the-Loop (HITL) approval, watchdog mechanisms, and audit logging. We also explore the possibility of using Large Language Model (LLM) applications as operator copilots—alarm interpretation, procedure assistance, knowledge retrieval—and actuating agents, each with distinct safety requirements. This integration layer forms the basis of Cosylab’s contribution to TwinRise, an EU-funded Digital Twin Engine project.
Software-Defined Networking (SDN) enables data plane programmability and allows for customised, high-speed packet processing that transcends the limitations of fixed-function hardware. This flexibility is increasingly vital for modern networks tasked with supporting intensive workloads, such as distributed AI training and real-time telemetry. However, supporting these workloads in practice is far from straightforward, as each technology operates within strict physical and architectural boundaries that ultimately determine what is feasible at deployment. This survey provides a detailed examination of the practical capability boundaries of prominent programmable data plane technologies, including Protocol-Oblivious Forwarding (POF), Programming Protocol-independent Packet Processors (P4), the extended Berkeley Packet Filter (eBPF), and the Network Programming Language (NPL). It traces their evolution and functional capabilities. We further explore the prevailing system designs and hardware platforms, spanning Application-Specific Integrated Circuits (ASICs) switches, Smart Network Interface Cards (SmartNICs) or Data Processing Units (DPUs), Field-Programmable Gate Arrays (FPGAs), and kernel or eXpress Data Path (XDP)-based software targets. A central concern of this survey is bridging the gap between theoretical programmability and what these platforms can realistically deliver in production. To that end, we map each hardware profile to concrete deployment scenarios, examining how these data planes are currently used across cloud data centres, edge and telco networks (including 5G and emerging 6G), and distributed AI and High-Performance Computing (HPC) clusters. Finally, we explore emerging high-speed communication fabrics and AI compute-enabled data planes, outlining the open challenges that will shape the next generation of intelligent networked systems.
Yaying Chen, S. Layeghy, Marius Portmann· IEEE Access· 0 citations
With the growing demand for artificial intelligence (AI) applications, high-performance and energy-efficient AI chips are needed to support the computation. However, architectural-level AI chip design, PPA evaluation, and power estimation remain challenging due to the exponential set of possible designs and the difficulty of accurately modeling the impact of diverse dataflows and workflows on the underlying hardware at the architectural-design stage. We propose a novel open-source framework named OSCAR, which, given a set of hardware and workload specifications, provides architecture-level power estimation and can also automatically generate Chisel and synthesizable RTL of the custom AI chip. Our contributions include (1) a flexible and hierarchical AI chip design space, software and hardware stack, and an RTL generator supporting dense, Transformer, Winograd, systolic, and reconfigurable architectures in one unified framework, (2) hierarchy-based data-sensitive power model using architectural-level toggling features, achieving 3.8% error and correlation coefficient R > 0.99 to post-synthesis power, outperforming state-of-the-art power estimation methods, (3) validation of our power model by performing design space exploration, finding designs with better Pareto-optimality, 2.5 × lower power or 2 × better runtime metrics, compared with using prior art power models, (4) a tape-out of an AI chip based on DSE results, with OSCAR modeling its power with over 90% accuracy.
J. Mok, Qijun Zhang, Di Pang et al.· ACM Transactions on Design A...· 0 citations
This work presents an end-to-end AI system that collapses the software-to-silicon stack into a single optimization loop, where hardware and software are co-designed and verified under one objective.
In HPC system management, the transition to modular architectures like OpenCHAMI requires standardization to ensure long-term interoperability. However, the consensus-building process required by open-source projects often operates on a different timeline than the deadline-driven operational needs of site administrators. This creates a synchronization challenge: teams must deliver functional software for immediate machine bring-up while ensuring alignment with future community standards. This paper details how the OpenCHAMI project utilized Fabrica, a custom code generator, to bridge this gap during the development of a Field Replaceable Unit Inventory Service. Fabrica decouples the API’s structural standards from its application logic, allowing the team to generate working prototypes for immediate testing at Los Alamos National Laboratory while retaining the flexibility to regenerate the service to match pending architectural decisions. We demonstrate how this approach enables parallel workflows and discuss its implications for improving Research Software Engineering productivity and facilitating AI-assisted development.
B. McDonald, Alex Lovell-Troy· Practice and Experience in A...· 0 citations
Artificial intelligence (AI) workflows increasingly span heterogeneous environments, from centralized high-performance computing (HPC) systems to resource-constrained edge devices. A primary hurdle in these pipelines is the configuration mismatch between development and deployment, often requiring researchers to manually rewrite scripts for specific edge requirements. This poster demonstrates an integrated management framework—showcasing both web-based and standalone user interface (UI) elements—powered by Tapis for the systematic testing and deployment of machine learning models. Building on existing cyberinfrastructure including the ML Field Planner for configuration, PATRA for model management, and the Cyberinfrastructure Knowledge Network (CKN) for telemetry, the framework provides a unified control interface. By utilizing the ML Edge Server as a consistent, pluggable runtime across the edge-to-center continuum, the system ensures that configurations and telemetry translate directly to field execution. This demonstration shows how a unified UI-driven workflow streamlines the transition from initial evaluation to deployment, ensuring operational consistency and reproducibility without manual script porting.
Manikya Swathi Vallabhajosyula, Gautam Gururaj Molakalmuru, Samuel Khuvis et al.· Practice and Experience in A...· 0 citations
Physical Unified Device Architecture (PUDA) is an AI-native hardware harness for self-driving laboratories (SDLs). Rather than building a human-centered graphical user interface (GUI) orchestration layer, PUDA creates a command-line runtime environment that lets agents observe, orient, decide, and act over experiments while hardware execution remains deterministic, atomic, and auditable. Headless by design, devices appear through discoverable command-line interfaces, JSON protocols are routed through a distributed messaging system, and command responses, data products, and reports are preserved as structured records. PUDA organizes protocols, runs, samples, measurements, and command logs into an AI-native data structure linked by run identifiers and timestamps, preserving provenance from submitted protocol through hardware response to resulting data products. PUDA separates scientific orchestration from physical operation and data telemetry: agents choose experiments, while PUDA executes validated commands and captures provenance-linked state, responses, and data. The contribution is not another optimizer, orchestrator, or recipe language. It is a practical execution and data environment for agentic SDLs; the broader physical AI implication is that PUDA provides an AI-native hardware harness for AI systems to interact with physical tools.
Zekun Ren, Hong-Fu Tan, Jiaen Yee et al.· 0 citations